Required in stage
Optional in stage
Second term
Both terms
Not organised
This year
Next year
Alternating years
External
Prerequisites
Identical coursesDigital Design Concepts (B-KUL-T2VDO2)
Cannot be taken as part of an examination contract
Geurts Luc (coordinator) | Geurts Luc | N. | Andries Martin (cooperator) | Cauwerts Yuri (cooperator) | Yudayev Max (cooperator) | LessMoreAims
Learning Outcomes:
- (K1) Basic scientific-disciplinary knowledge and comprehension
- (I1) Analyze and solve problems
- (I2) Design and/or develop
- (P1) Operationalisation
- (G1) Information gathering and processing
- (G2) Communication with engineers and non-engineers
- (G3) Critical thinking
- (G5) Professionalism
Learning Objectives:
Lectures
The student:
- knows the functionality of basic digital building blocks. (K1)
- can describe the functionality of a simple digital circuit through a schematic and a signal diagram. (K1)
- can design a (synchronous) digital circuit with a specific function. (K1, I1, I2)
- can describe a sequential function in the form of an FSM (Finite State Machine) and convert it to a digital system composed of logic gates and flip-flops. (K1, I1, I2)
- knows the principles and functioning of different memories. (k1)
- knows the basic characteristics of semiconductor technology and reconfigurable logic. (K1)
Lab sessions
The student:
- has insight into the behaviour of elementary digital building blocks (modules). (K1)
- knows the basic architecture of an FPGA and can use it to implement a digital system (K1, I2)
- has insight into the design flow of a digital circuit. (K1)
- can describe the functionality of a digital circuit in HDL in a structured manner. (K1, I1, I2, G2)
- can design a testbench to verify the functionality of a digital circuit described in HDL using simulations and interpret the results in a critical manner. (K1, I1, I2, G3, P1)
- can convert a digital circuit described in HDL in a contemporary EDA environment using logic synthesis into an implementable description for FPGA architectures . (K1, I1, I2, P1)
- can use system testing to verify and critically interpret the functionality of a digital system. (K1, I1, I2, G3, P1)
- can plan his/her activities taking into account given deadlines. (G5)
- can independently look up and interpret information sources. (G1)
Previous knowledge
Basic concepts of electronics and elementary components: capacitor, transistor
Order of Enrolment
Mixed prerequisite:
You may only take this course if you comply with the prerequisites. Prerequisites can be strict or flexible, or can imply simultaneity. A degree level can be also be a prerequisite.
Explanation:
STRICT: You may only take this course if you have passed or applied tolerance for the courses for which this condition is set.
FLEXIBLE: You may only take this course if you have previously taken the courses for which this condition is set.
SIMULTANEOUS: You may only take this course if you also take the courses for which this condition is set (or have taken them previously).
DEGREE: You may only take this course if you have obtained this degree level.
FLEXIBLE(T1AEA1) OR FLEXIBLE(T1AEA2)
The codes of the course units mentioned above correspond to the following course descriptions:
T1AEA1 : Elektronica
T1AEA2 : Electronics
This course unit is a prerequisite for taking the following course units:
T2VCA1 : Computerarchitecturen
T2VCA2 : Computer Architectures
T3WDO2 : Complex Digital Design
Identical courses
This course is identical to the following courses:
T2VDO1 : Digitale ontwerpprincipes
B3075N : Digitale ontwerpprincipes
ZA0218 : Digitale ontwerpprincipes
YI1432 : Digitale ontwerpprincipes
Is included in these courses of study
- Bachelor of Engineering Technology (Leuven) (Core Programme Electronics and ICT Engineering) 180 ects.
- Bachelor of Engineering Technology, 2+2 Module (Leuven) (Core Programme Electronics and ICT Engineering) 180 ects.
Activities
3 ects. Digital Design Concepts: Lecture (B-KUL-T2hDO2)
Content
- Combinatorial design
- Logic gates, coding and Boolean algebra
- Function simplification and implementation
- Combinatorial circuits (Half adder & Full adder, Coders/Decoders, Multiplexer, comparator,…)
- Power consumption, delays and loading
- Logic functions in semiconductors (CMOS) and reconfigurable logic
- Sequential design techniques
- Latches and flip-flops (eg. SR-latch, D-Flip-flop)
- Setup – Hold times
- Counters and shift registers
- Finite State Machines (Moore, Mealy)
- Memories
- ROM
- SRAM
- DRAM
- Non-volatile memories (Flash, MRAM, …)
Format: more information
Traditional lecture
2 ects. Digital Design Concepts: Lab Session (B-KUL-T2pDO2)
EnglishFormat: Practical
24 
First termN. | Andries Martin (cooperator) | Cauwerts Yuri (cooperator) | Yudayev Max (cooperator) Content
- Design methodology for digital systems
- FPGA architectures
- Hardware Description Language (VHDL/Verilog)
- Design for synthesis
- Design for verification
- Design and verification of combinatorial and sequential systems
Evaluation
Evaluation: Digital Design Concepts (B-KUL-T72146)
Explanation
1. Calculation of the final mark
The final mark of this course is calculated based on the published component marks with the following weighting factors:
Component mark for lectures: 60%
Component mark for lab sessions: 40%
The only exception to this rule is described in the complementary regulation of the Faculty of Engineering Technology to article 66 in the Regulations on Education and Examinations.
2. Calculation of the published component marks
The component mark for ‘lectures’ is a whole number between 0 and 20. It is an evaluation of the student’s performance based on the results of the exam during the examination period. The evaluation takes place via a closed book written exam during the examination period.
The component mark for the lab sessions is a whole number between 0 and 20. It is an evaluation of the student’s performance based on the permanent evaluation of the labs and a final presentation.
3. Absences
Unauthorized absence during the exam leads to NA as a component mark for 'lectures'.
Remaining absent from a lab session without valid reason will result in 0 on 20 for that session. If you remain absent without valid reason for 2 or more lab sessions, you get a component mark NA for the lab sessions. Absences with valid reason need to be communicated and be caught up as soon as possible.
For absences during the teaching weeks, please contact the education ombuds on the first day of your absence. If you missed one or more obligatory sessions, please contact your professor as soon as possible and certainly within a week. For absences within the exam period, please contact the exam ombuds on the first day of your absence.
4. Partial transfers and re-examinations
Component marks of at least 10/20 published in the academic progress file are transferred to the next examination period within the same academic year and to the following academic years, except for temporary marks and marks for intermittent tests.
When needed, additional information on the evaluation activities is provided during the lessons and/or made available on the Toledo pages of the course. Further if the university decides that it is confronted with situations of general force majeure or situations where the safety and health of members of the academic community of KU Leuven may be endangered and changes to the teaching and evaluation activities occur as a result, these changes will be communicated via Toledo.
Information about retaking exams
This course unit allows partial mark transfers in case of partial pass mark:
- T2hDO2 - Digital Design Concepts: Lecture (during and beyond academic year)
- T2pDO2 - Digital Design Concepts: Lab Session (during and beyond academic year)
This course unit allows partial mark transfers in case of partial pass mark:
- Digital Design Concepts: Lectures (during and beyond academic year)
- Digital Design Concepts: Lab Sessions (during and beyond academic year)
Digital Design Concepts: Lectures
Same modalities as for the first examination opportunity.
Digital Design Concepts: Lab Sessions
Individual take-home assignment with oral defense during the examination period. For specific details, the student needs to contact the course coordinator.