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Complex Digital Design (B-KUL-T3WDO2)

3 ECTSEnglish38 Second termCannot be taken as part of an examination contract
Geurts Luc (coordinator) |  N. |  Andries Martin (cooperator) |  Cauwerts Yuri (cooperator) |  Cui Songqiao (cooperator) |  Yudayev Max (cooperator)  | LessMore
OC Elektronica-ICT - Campus Groep T Leuven

Aims

Learning Outcomes:

  • (K1) Basic scientific-disciplinary knowledge and comprehension
  • (I1) Analyze and solve problems
  • (I2) Design and/or develop
  • (P1) Operationalisation
  • (G1) Information gathering and processing
  • (G2) Communication with engineers and non-engineers
  • (G3) Critical thinking
  • (G5) Professionalism

 

Learning Objectives:

Lectures

The student:

  • can design a digital circuit based on predefined requirements (including speed, synchronous design methodology, interfacing to synchronous environments) (K1, I1, I2)
  • knows the problems and solutions for clock domain synchronization (K1)
  • knows the implementations of arithmetic logic functions (K1)
  • knows the principles of “design for testability” and can apply them. (K1, I1, I2)

 

Lab sessions

The student:

  • can interpret the specification of a new digital circuit from applied scientific research. (G1, G3)
  • can design a digital circuit based on (reusable) modules. (P1, I1, G3)
  • can apply the synchronous design methodology for digital circuits. (P1, K1, I1, I2)
  • can develop a digital system using contemporary EDA tools at architecture level: describe functionality in HDL code, simulate with appropriate testbenches, verify (logic synthesis) and implement (FPGA). (K1, I1, I2, P1)
  • can determine the critical path of an implemented digital circuit. (K1, P1)
  • can plan his/her activities taking into account given deadlines. (G5)

Previous knowledge

Combinational and sequential circuits and design techniques

Order of Enrolment

Mixed prerequisite:
You may only take this course if you comply with the prerequisites. Prerequisites can be strict or flexible, or can imply simultaneity. A degree level can be also be a prerequisite.
Explanation:
STRICT: You may only take this course if you have passed or applied tolerance for the courses for which this condition is set.
FLEXIBLE: You may only take this course if you have previously taken the courses for which this condition is set.
SIMULTANEOUS: You may only take this course if you also take the courses for which this condition is set (or have taken them previously).
DEGREE: You may only take this course if you have obtained this degree level.


FLEXIBLE(T2VDO2) OR FLEXIBLE(T2VDO1)

The codes of the course units mentioned above correspond to the following course descriptions:
T2VDO2 : Digital Design Concepts
T2VDO1 : Digitale ontwerpprincipes

This course unit is a prerequisite for taking the following course units:
T4VRD2 : R&D Experience

Identical courses

This course is identical to the following courses:
B3075X : Complex digitaal ontwerp
ZA0301 : Complex digitaal ontwerp

Is included in these courses of study

Activities

2 ects. Complex Digital Design: Lecture (B-KUL-T3hDO2)

2 ECTSEnglishFormat: Lecture18 Second term
N.
OC Elektronica-ICT - Campus Groep T Leuven

Content

  • Advanced sequential design
    • Clock domains and clock distribution
    • Clock domain synchronization and resets
    • Clock generation (PLL, crystals, DDS)
    • Timing analysis and power consumption
  • Arithmetic functions
    • Adders (Rippel carry adder, carry look ahead, carry save)
    • Multipliers
    • MAC
    • Overflow and saturation
  • Testing of digital systems
    • Design for testability
    • Test methods and algorithms (Scan Flip-flops, BIST, JTAG, ATPG)

1 ects. Complex Digital Design: Lab Session (B-KUL-T3pDO2)

1 ECTSEnglishFormat: Practical20 Second term
N. |  Andries Martin (cooperator) |  Cauwerts Yuri (cooperator) |  Cui Songqiao (cooperator) |  Yudayev Max (cooperator)
OC Elektronica-ICT - Campus Groep T Leuven

Content

  • Advanced design methodologies for digital systems
  • Hardware Description Language (Verilog)
    • Serial communication interfaces
    • Arithmetic logic blocks
  • Verification and FPGA implementation

Evaluation

Evaluation: Complex Digital Design (B-KUL-T72165)

Type : Partial or continuous assessment with (final) exam during the examination period
Description of evaluation : Written, Presentation, Participation during contact hours
Type of questions : Multiple choice, Open questions

Explanation


1. Calculation of the final mark

The final mark of this course is calculated based on the published component marks with the following weighting factors:

    Component mark for lectures: 65%

    Component mark for lab sessions: 35%

The only exception to this rule is described in the complementary regulation of the Faculty of Engineering Technology to article 66 in the Regulations on Education and Examinations.

2. Calculation of the published component marks

The component mark for ‘lectures’ is a whole number between 0 and 20. It is an evaluation of the student’s performance based on the results of the exam during the examination period. The evaluation takes place via a closed book written exam during the examination period.

The component mark for the lab sessions is a whole number between 0 and 20. It is an evaluation of the student’s performance based on the permanent evaluation of the labs and a final presentation.

3. Absences

Unauthorized absence during the exam leads to NA as a component mark for 'lectures'.

Remaining absent from a lab session without valid reason will result in 0 on 20 for that session. If you remain absent without valid reason for 2 or more lab sessions, you get a component mark NA for the lab sessions. Absences with valid reason need to be communicated and be caught up as soon as possible.

For absences during the teaching weeks, please contact the education ombuds on the first day of your absence. If you missed one or more obligatory sessions, please contact your professor as soon as possible and certainly within a week. For absences within the exam period, please contact the exam ombuds on the first day of your absence.

4. Partial transfers and re-examinations

Component marks of at least 10/20 published in the academic progress file are transferred to the next examination period within the same academic year and to the following academic years, except for temporary marks and marks for intermittent tests.

 

When needed, additional information on the evaluation activities is provided during the lessons and/or made available on the Toledo pages of the course. Further if the university decides that it is confronted with situations of general force majeure or situations where the safety and health of members of the academic community of KU Leuven may be endangered and changes to the teaching and evaluation activities occur as a result, these changes will be communicated via Toledo.

Information about retaking exams

This course unit allows partial mark transfers in case of partial pass mark:

  • T3hDO2 - Complex Digital Design: Lecture (during and beyond academic year)
  • T3pDO2 - Complex Digital Design: Lab Session (during and beyond academic year)

Complex Digital Design : Lectures

Same modalities as for the first examination opportunity.

Complex Digital Design : Lab Sessions

Individual take-home assignment with oral defense during the examination period. For specific details, the student needs to contact the course coordinator.