Objectives

Upon completion of this course, the student

* has insight in the close relationship between design and verification for digital logic and systems on a chip

* has insight in the multiple methods to assist in verifying the functionality of a given digital design:
- Linting / Code Review
- Clock Domain Crossing (CDC)
- RTL / Netlist Simulation
- Emulation
- Formal Property Verification (FPV)

* has insight in multiple industry standard methods to make a given design more robust and help avoid or eliminate edge-cases when taking the digital design through the full ASIC development pipeline: 
- Formal Verification
- Static Timing Analysis (STA)
- Back-end checks: Cross talk, IR drop, Layout vs Schematic (LVS), Design rule checks

* has insight in multiple approaches for testbenches:
- visual verification (checking the waves) 
- golden reference files, compare with model
- combine with inverse model (eg. TX - RX)
- direct testing vs randomization
- assertion based verification
- code coverage, functional coverage, cover points
- interpreting the results of a testbench and debugging the design

* has insight in and can create, implement and modify a UVM testbench

* has insight in simulating analog-mixed signal designs:
- how the simulators work, with regard to an analog vs digital solver
- requirements management and test runs
- development of a mixed-signal chip, from concept to tapeout

* has insight in the design and verification of a System on chip design:
- verification of software in an SoC
- using different layers of abstraction by means of behavioural modelling

* can utilize the learning content during the hands-on workshops

Educational quality of the study programme

Here you can find an overview of the results of the COBRA internal quality assurance method.

Educational quality at study programme level

Blueprint

Educational quality at university level

• Consult the documents on educational quality available at university level.

More information?

• More information on the educational quality at KU Leuven
• More information on the available documents